; bhtsddr.inf - [default_cfg_GG8] section ;Mode values: 0=SDMA, 1=ADMA2, 2=ADMA2+INF, 4=ADMA3, 5=ADMA3+INF, 6=ADMA3+MIX, 0xF=PIO ;0x8000000F = bit31 valid + mode 0xF = PIO (no DMA, CPU transfer) HKR,"Parameters\GG8", "test_dma_mode_setting",0x00010001, 0x8000000F
3.2 代码修改
修改 1: cfgmng.c - 缓冲区映射配置
PIO 模式需要 CPU 直接访问 SRB 数据缓冲区,必须设置 MapBuffers = STOR_MAP_ALL_BUFFERS_INCLUDING_READ_WRITE。
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boolcfg_dma_need_sdma_like_buffer(u32 dma_mode) { // These modes require MapBuffers = STOR_MAP_ALL_BUFFERS_INCLUDING_READ_WRITE // because they need CPU-accessible virtual addresses for data buffers: // - SDMA modes: use internal aligned buffers and copy data // - PIO mode: CPU directly transfers data, no DMA involved if((CFG_TRANS_MODE_ADMA2_SDMA_LIKE == dma_mode) || (CFG_TRANS_MODE_ADMA3_SDMA_LIKE == dma_mode) || (CFG_TRANS_MODE_SDMA == dma_mode) || (CFG_TRANS_MODE_ADMA_MIX_SDMA_LIKE == dma_mode) || (CFG_TRANS_MODE_PIO == dma_mode)) // ← 新增 PIO 模式 return TRUE; else return FALSE; }
修改 2: host.c - 传输模式初始化
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case CFG_TRANS_MODE_PIO: // PIO mode - no DMA, CPU transfers data directly host_dma_select(host, TRANS_PIO); DbgErr("DMAR_DIAG: *** PIO MODE ENABLED (mode=0xF) ***\n"); DbgErr("DMAR_DIAG: No DMA transfer - CPU will transfer data directly\n"); break;
修改 3: reqmng.c - 请求路由
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// for PIO case, forward the request to gen io if(pdx->cfg->host_item.test_dma_mode_setting.dma_mode == 0xF) { srb_ext->req.gen_req_t.code = GEN_IO_CODE_PIORW; srb_ext->req.gen_req_t.arg1 = sec_addr; srb_ext->req.gen_req_t.arg2 = sec_cnt; result = req_gen_io_add(pdx, srb_ext); }
BHT-ERROR : DMAR_DIAG: *** PIO MODE ENABLED (mode=0xF) *** BHT-ERROR : DMAR_DIAG: No DMA transfer - CPU will transfer data directly BHT-ERROR : DMAR_DIAG: This mode is for DMA remapping (IOMMU) compatibility testing